1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to an interconnection in a complementary static RAM and the like and a method of manufacturing a static memory cell.
2. Description of the Background Art
FIGS. 18 and 19 show an example of N-type well-source structure in a memory cell of a prior-art Full CMOS SRAM, for example, as disclosed in Japanese Patent Publication 1-44023. FIG. 18 is a schematic plan view illustrating a pattern wiring of a memory cell in such an SRAM, and FIG. 19 is a cross section of FIG. 18 along the line C-C'.
In FIGS. 18 and 19, a one-bit memory cell 1P of a static RAM, metal wires (1AL) 2P and 14P for making a contact, contact holes 3P, 15P, 22 and 23, a GND wiring layer 5P to which a ground potential is applied, N.sup.+ -type diffusion regions 6P and 8P, P.sup.+ -type diffusion regions 7P and 9P, a silicon oxide film 10P serving as an insulation film, an insulator 11P for electrically isolating the diffusion regions 6p and 7P and the like, an N-type well 12P to form a PMOS region and a P-type substrate 13P are shown.
Referring to FIG. 19, a path for supplying the static memory cell 1P with a power supply potential (V.sub.DD) will be described. When the power supply potential V.sub.DD is applied to the metal wire 2P by an external wire not shown to which the power supply potential is applied, the power supply potential V.sub.DD is applied to the N well 12P from the metal wire 2P through the contact hole 3P and the N.sup.+ -type diffusion region 6P, and further applied to the P.sup.+ -type diffusion region 7P serving as a source region of PMOS transistor from the N well 12P through the N.sup.+ -type diffusion region 8P, the contact hole 22, the metal wire 14P and the contact hole 15P.
The N-type well-source structure is effective for improvement in withstand latch-up voltage, as already recited in the Japanese Patent Publication 1-44023. Specifically discussing, an emitter potential of a PNP transistor consisting of the P-type substrate 13P, the N well 12P and the P.sup.+ -type diffusion region 7P, which is supplied through the N well 12P, the N.sup.+ -type diffusion region 8P, the contact hole 22 and the metal wire 14P, is necessarily lower than a base potential of the PNP transistor which is the same as the potential at the N well 12P. Therefore, no forward bias is applied between the emitter and base of PNP transistor, and accordingly a latch-up can be prevented.
The prior-art Full CMOS SRAM with the above structure can prevent a latch-up, but raises the following problem. Specifically, as shown in the prior art of FIGS. 18 and 19, the N.sup.+ -type diffusion region 8P and the P.sup.+ -type diffusion region 7P form a PN junction and are not electrically connected. To supply the source region of PMOS transistor in the N well 12P with a source potential, the two diffusion regions 7P and 8P need to be electrically connected by providing the contact hole 22, the metal wire 14P and the contact hole 15P on the way of the supply path. Provision of such interconnection region disadvantageously results in enlargement of the layout size.
For example, sizes L1 and L2 shown in FIG. 19 have to be set depending on diameters of the contact holes 22 and 15P, respectively. To arrange the contact holes 22 and 15P with relatively low accuracy for manufacturing simplicity, the sizes L1 and L2 need to be set sufficiently larger than the diameters of the contact holes 22 and 15P, respectively. As shown in FIG. 18, also in a direction of Y, the width W of the diffusion regions 7P and 8P need to be set sufficiently larger than the diameters of the contact holes 15P and 22, for manufacturing convenience. Therefore, the surface area of the N.sup.+ -type diffusion region 8P and the like must be inevitably larger.
The problem as above rises not only in a case of N well-source structure shown in FIGS. 18 and 19 but also in a case of ground interconnection of memory cells of Full CMOS SRAM with P-type well-source structure.
Accordingly, provision of well-source structure in SRAM memory cells with Full CMOS structure, generally, ensures improvement in withstand latch-up voltage, but on the other hand, disadvantageously increases the layout size of the diffusion regions to form a well-source structure.